1. Field of the Invention
The present invention relates to a printhead element substrate suitable for an inkjet printhead, and a printhead, head cartridge, and printing apparatus using the element substrate.
2. Description of the Related Art
Generally, electrothermal transducers (heaters) of a printhead and their driving circuits in an inkjet printing apparatus are formed on a single substrate using a semiconductor process technology, as described in U.S. Pat. No. 6,290,334.
FIG. 3 is a view schematically showing a semiconductor element substrate of this type for an inkjet printhead.
Referring to FIG. 3, heaters and driving circuits are integrally built in an element substrate 100 by a semiconductor process technology. Reference numeral 101 denotes a driver & heater array in which a plurality of heaters and a plurality of driver transistors serving as switching elements which are provided in correspondence with the heaters and switch whether to direct a current flow to the heaters are arrayed. Ink supply ports 102 supply ink from the lower surface of the element substrate.
A shift register (S/R) 103 temporarily holds print data. A decoder 107 outputs a block enable signal to time-divisionally drive blocks of the heaters in the driver & heater array 101. Input circuits 104 include buffer circuits to input digital signals to the shift registers 103 and decoders 107. Input terminals 110 include a Vdd terminal to input a logic element voltage Vdd, a CLK terminal to input a clock (CLK) signal, and a DATA terminal to input print data (DATA).
The digital circuits such as the shift registers and decoders are driven by a digital power supply voltage (voltage VDD). A level converter 116 converts a digital signal such as the VDD voltage driving signal into a VHT voltage signal to be given to the gate of each driver transistor. The voltage VHT is higher than the voltage VDD. A VHT voltage generation circuit 130 generates the voltage VHT to be supplied to the level converter 116 by stepping down a heater driving power supply voltage (VH). An AND circuit 119 serves as a heater selection circuit which calculates the logical product of a block enable signal and a print data signal. The AND circuit 119 includes, e.g., a buffer as needed.
FIG. 5 is a timing chart for explaining a series of operations of sending a print data signal to the shift register 103 and supplying a current to the heaters to drive them.
Print data is input to the DATA_A and DATA_B terminals in synchronism with the pulse of a clock signal input to the CLK terminal. The shift register 103 temporarily stores the input print data. A latch circuit holds the print data in accordance with a latch signal input to an LT terminal. After that, the logical product of a block enable signal to select a heater group divided into desired blocks and the signal of print data (print data signal) held according to the latch signal is calculated. The signal of the calculated logical product synchronizes with an HE signal that directly determines the current driving time so that a current flows to desired heaters. The series of operations is repeated for the respective blocks, thereby executing printing.
FIG. 4A is an equivalent circuit diagram corresponding to one segment having one heater and a corresponding driver in a conventional printing element. FIG. 4B is an equivalent circuit diagram corresponding to one bit of the shift register and latch circuit to temporarily store print data.
The block enable signal input to an AND circuit 201 is supplied from the decoder 107. The block enable signal selects each heater group corresponding to one of divided blocks. The print data signal input to the AND circuit 201 is a signal input to the shift register 103 and held according to the latch signal. To selectively drive the heaters, the AND circuit 201 serving as a heater selection circuit calculates the logical product of the block enable signal and print data signal.
Reference numeral 205 denotes a VH power supply line; 206, a heater; and 207, a driver transistor serving as a switching element to direct a current flow to the heater 206. An inverter circuit 202 receives and buffers the output from the AND circuit 201. A VDD power supply line 203 serves as a power supply of the inverter circuit 202. A VHT power supply line 204 serves as a power supply to apply a voltage to the gate of the driver transistor 207. An inverter circuit 208 receives the voltage from the VHT power supply line. The inverter circuit 208 serves as a buffer to receive the buffer output from the inverter circuit 202.
The inverter circuit 202, shift register 103, and the like are digital circuits in general and operate in accordance with a low or high pulse. A heat enable signal (HE) to designate a heater driving period is also a digital signal. Signal exchange with an external device is done by a low or high logic pulse. The voltage amplitudes of the digital signals are generally 0 V/5 V or 0 V/3.3 V. The power supply voltage of the digital circuits is VDD only. The above-described block enable signal and print data signal are input to the AND circuit 201 as the pulse of the voltage VDD and then input to the inverter circuit 208 of the next stage through the buffer formed from the two inverter circuits 202.
The resistance value in the ON state, i.e., so-called ON resistance of the driver transistor 207 is preferably as low as possible. In this case, since the power consumed by circuits except the heaters is minimized, an increase in the substrate temperature can be prevented, and stable printhead driving is possible. If the ON resistance of the driver transistor 207 is high, a current flows to this portion to make the voltage drop large. This requires to apply a higher voltage to the heater, and the power is wasted.
To reduce the ON resistance of the driver transistor 207, it is necessary to raise the voltage to be applied to the gate of the driver transistor. For this purpose, in the circuit shown in FIG. 4A, it is necessary to convert the voltage into a pulse voltage higher than the voltage VDD. The circuit shown in FIG. 4A has the power supply line 204 of the voltage VHT higher than the voltage VDD so that the buffer circuit including the inverter circuit 208 converts the block enable signal input by the pulse of the voltage VDD into a pulse of the voltage VHT. After conversion, the pulse of the voltage VHT is applied to the gate of the driver transistor 207. That is, signal exchange with an external device and signal processing in the internal digital circuits are done in accordance with the pulse of the voltage VDD (logic circuit driving voltage). In the circuit shown in FIG. 4A, an amplitude conversion circuit (level converter) which converts the voltage into the pulse of the voltage VHT (switching element driving voltage) is added to each segment immediately before driving the gate of the driver transistor 207. In FIG. 3, reference numerals 116 denote the level converters of the plurality of segments.
Generally, a printhead has a plurality of segments arrayed at a high density. When the segments are arranged at a density of, e.g., 600 dpi, the array-direction width per segment is limited to about 42.3 μM. To arrange, in this pitch, all circuits for driving the segments in FIG. 4A, the size in a direction perpendicular to the array direction of the segments needs to increase.
FIG. 9 is an equivalent circuit diagram showing the detailed structure of the level converter portion in FIG. 4A. As is apparent from FIG. 9, since the level converter portion (especially level conversion unit) includes a number of transistors, the area of the necessary element substrate increases.
However, when a level converter is added to each segment, the length of the segment increases. This leads to an increase in the size of the element substrate for the printhead, resulting in an increase in cost. More specifically, in the above-described substrate structure, the element substrate spreads in the direction perpendicular to the segment array direction, and the size of the element substrate conspicuously increases. When a level converter is added to each of, e.g., 256 segments of a printhead, at least 256 inverters are necessary, resulting in an increase in cost.
To solve this problem, U.S. Publication No. 2006/0209131 discloses a circuit arrangement which converts a logic circuit driving voltage into a printing element driving voltage without increasing the length in the direction perpendicular to the segment array direction.
FIG. 10 is a view for explaining the arrangement of U.S. Publication No. 2006/0209131. The same reference numerals as in FIG. 3 denote the same parts in FIG. 10, and a description thereof will not be repeated unless they are particularly different from FIG. 3.
In FIG. 10, the level converter 116 is provided in the output stage of each decoder 107 and the output stage of each shift register 103.
FIG. 2A is an equivalent circuit diagram, different from FIG. 4A, corresponding to one segment having one heater and a corresponding driver in a conventional printing element. FIG. 2B is an equivalent circuit diagram, different from FIG. 4B, corresponding to one bit of the shift register and latch circuit to temporarily store print data.
In the element substrate 100 in FIG. 10, the level converter is added to the output portion of each of the shift registers 103 and decoders 107, unlike the element substrate 100 in FIGS. 3 and 4A in which the level converter is added to each segment. That is, the voltage rises before the AND circuit 201 calculates the logical product of the output signal (block enable signal) from the decoder 107 and the output signal (print data signal) from the shift register 103. Hence, as shown in FIG. 2A, a pulse signal stepped up to the voltage VHT is input to each segment. This obviates the level converter of each segment so that the area of the element substrate can be reduced.
Since a high voltage is applied to the AND circuit 201 that calculates a logical product for each segment, high-voltage-proof elements are necessary as transistors included in the AND circuit 201. Conventionally, the transistors are formed from low-voltage-proof elements because only a low voltage corresponding to the logic circuit driving voltage is applied to this portion. In the technique disclosed in U.S. Publication No. 2006/0209131, the breakdown voltage of this portion is made higher than that for the transistors of the remaining logic circuits. More specifically, high-voltage-proof elements are used as the transistors included in the AND circuit.
When such high-voltage-proof elements (MOS transistors) are used, each transistor becomes larger than a low-voltage-proof transistor. However, the size of the element substrate 100 can be reduced because the number of level converters can be small, and they can be located far from the segments.
FIG. 2B is a circuit diagram showing the arrangements of the shift register 103 and level converter 116. The level converter (amplitude conversion circuit) is added to the output stage of the shift register 103 shown in FIG. 4B to convert the pulse voltage from the voltage VDD to the voltage VHT.
The number of output stages of the shift register 103 or decoder 107 is determined by the division count in time-divisionally driving all segments. The division count is about 8 to 32. For example, when 256 segments are divided into 16 blocks (each block includes 16 segments), the necessary number of level converters 116 is 16×2 (shift register side and decoder side)=32. The number greatly decreases as compared to the arrangement with the level converters 116 added to all segments. For this reason, the length of the element substrate 100 in the direction perpendicular to the segment array direction can decrease. The level converters 116 added to the shift registers 103 and decoders 107 increase the length of the element substrate 100 in the array direction. However, this increase is insignificant relative to the decrease in the length in the perpendicular direction. The total area of the element substrate 100 decreases.
An inkjet printing apparatus is required to execute printing at a higher speed. For this reason, the number of orifices of the printhead increases, and the density of the orifices becomes high. Since the number of ink colors, the number of ink supply ports, and the number of orifice arrays also increase, the area of the element substrate becomes large.
FIG. 12 is a view showing the arrangement and vertical positional relationship of two adjacent segments on an element substrate with a segment density of 1,200 dpi. On the element substrate, heaters 206a for a medium discharge amount (2.5 pl) and heaters 206b for a small discharge amount (1 pl) are arranged at a pitch of 1,200 dpi from the side close to the ink supply port 102. Orifices are schematically illustrated on the heaters. These heaters are connected to transistors 207a and 207b by wirings (not shown).
Corresponding level converters 116a and 116b are arranged on the side far from the ink supply port. When the pitch is 1,200 dpi, the array-direction width per segment is only 21 μm. For this reason, it is impossible to arrange two level converters in the segment array direction. Two level converters are arranged in the segment array direction and in the vertical direction. Since the area of a level converter is large, the width of the element substrate increases.
The arrangement disclosed in U.S. Publication No. 2006/0209131 can generally reduce the area of the element substrate but poses several problems in a recently required long-length high-definition head. In FIG. 10 which explains U.S. Publication No. 2006/0209131, the wiring of the high-voltage pulse signal output from the level converter 116 has a long length from one end to the other end of the element substrate in the long side direction. For this reason, consideration from the viewpoint of design must be given to radiation noise. More specifically, it is necessary to ensure a large space between the wirings or pass GND wirings between the wirings.
Recently, it is required to arrange a number of segments at a high density. For example, it is necessary to arrange 512 orifices at 1,200 dpi or 1,024 orifices at 2,400 dpi. When the number of segments increases, the number of wirings for the data signal and the number of wirings for the block enable signal increase. This may also raise the increase ratio of the chip width due to the above-described radiation noise measure and reduce the shrink effect generated by decreasing the number of level converters. FIG. 13 shows this state.
FIG. 13 is a view showing the arrangement and vertical positional relationship of two adjacent segments. On the element substrate, the heaters 206a for a medium discharge amount (2.5 pl) and the heaters 206b for a small discharge amount (1 pl) are arranged at a pitch of 1,200 dpi from the side close to the ink supply port 102. Orifices are schematically illustrated on the heaters. These heaters are connected to the transistors 207a and 207b by wirings (not shown). An AND circuit 119 which is operated by a high-voltage signal exists next to each transistor. Reference numeral 118 denotes wirings for a print data signal and block enable signal. The wirings 118 receive a high-voltage pulse signal, as described above. Hence, the high-voltage signal wirings are spaced apart from each other, and GND wirings are arranged between them, as indicated by dotted lines. The area occupied by the wirings 118 increases and cancels the width reducing effect obtained by eliminating level converters near the transistors.